This invention relates to an improved sense circuit capable of sensing a small input current signal and producing a large voltage output swing, to a novel negative-resistance circuit, load circuit, level shifter, and amplifier that can be used in the sense circuit, and to a Schmitt trigger employing the negative-resistance circuit.
The well-known advantage of using current signals with small voltage swings in integrated circuits is that these signals can be transmitted quickly over long interconnecting lines. In a read-only memory (ROM), static random-access memory (SRAM), or dynamic random-access memory (DRAM), for example, current signals can be used for rapid transfer of data over data lines. Sense circuits must then convert the data signals from current to voltage form in order to drive transistors, and to enable the memory device to output the data in a standard voltage-signal mode.
A conventional sense circuit of this type comprises the following elements coupled in series between a power-supply terminal and ground: a first resistance, an input terminal, a transistor, an output terminal, and a second resistance. The transistor is controlled by an amplifier that receives input from the output terminal, creating a positive feedback loop. Positive feedback enables a small change in current at the input terminal to produce a large voltage change at the output terminal.
FIG. 1 shows part of a DRAM using this conventional sense circuit. The symbols V.sub.CC and GND indicate the power-supply potential and ground, respectively.
The switching circuit 1 is one of a large number of similar switching circuits coupled to a data line DL, which feeds the input terminal IN of a sense circuit 2. The output terminal OUT of the sense circuit 2 is coupled to a next-stage differential voltage amplifier (not shown in the drawing).
The switching circuit 1 comprises n-channel metal-oxide-semiconductor field-effect transistors (hereinafter, N-MOSFETs) 1a and 1b coupled in series between data line DL and ground. The gate of N-MOSFET 1a is coupled to a column select line CL; the gate of N-MOSFET 1b is coupled to a bit line BL.
The sense circuit 2 has been divided for explanatory purposes into three blocks: a data-line load circuit 3, a current-to-voltage converter 4, and an inverting amplifier 5. In the load circuit 3, a p-channel metal-oxide-semiconductor field-effect transistor (hereinafter, P-MOSFET) 3a with its gate coupled to ground provides a load resistance between V.sub.CC and the input terminal IN. In the current-to-voltage converter 4, a P-MOSFET 4a and N-MOSFET 4b are coupled in series between the input terminal IN and ground. The drain of P-MOSFET 4a, the drain and gate of N-MOSFET 4b, and the output terminal OUT are coupled at a node N.sub.1. The N-MOSFET 4b provides a current-sensing resistance between node N.sub.1 and ground. The gate of P-MOSFET 4a is coupled to a node N.sub.2.
The inverting amplifier 5 has an input node A.sub.in coupled to node N.sub.1 and an output node A.sub.out coupled to node N.sub.2, and comprises a P-MOSFET 5a and N-MOSFET 5b coupled in series between V.sub.CC and ground. The gate and drain of P-MOSFET 5a are coupled to the output node A.sub.out. The drain of N-MOSFET 5b is coupled to the output node A.sub.out, and its gate is coupled to the input node A.sub.in.
During normal operation, the data line DL is biased to a potential near V.sub.CC, the potential being controlled by the current flow through the load P-MOSFET 3a. A certain bias current I flows from V.sub.CC through the load circuit 3 to the current-to-voltage converter 4. Little or no current flows between the load circuit 3 and data line DL.
If read access results in activation of CL and BL, turning on transistors 1a and 1b in the switching circuit 1, then some of this bias current I is diverted from the current-to-voltage converter 4 to the data line DL. The resulting reduction -.DELTA.I in current flow through the current-to-voltage converter 4 reduces the potential at node N.sub.1, so the potential at the input terminal A.sub.in of the inverting amplifier 5 falls. The potential at the output terminal A.sub.out (node N.sub.2) therefore rises, reducing the conductance of P-MOSFET 4a. Current flow through the current-to-voltage converter 4 is thereby reduced still further, setting up positive feedback that quickly produces a large voltage swing at the output terminal OUT.
The reduction in current flow through the current-to-voltage converter 4 is partly balanced by the increased current flow on the data line DL, so the change in the current flowing through the load circuit 3 is small. The change in potential at the input terminal IN is therefore slight; the voltage swing on the data line DL is kept small. Ideally, the current increase .DELTA.I on the data line DL equals the current decrease -.DELTA.I in the current-to-voltage converter 4, as shown in FIG. 1, in which case a large output voltage swing is obtained with no voltage swing on the data line LD.
The conventional sense circuit 2, however, is not ideal. It has problems from the standpoints of both design and operation, as discussed next.
One problem arises from the similarity between the left side of the circuit, comprising the load 3 and current-to-voltage voltage converter 4 and denoted as circuit A in FIG. 1, and the right side, comprising the inverting amplifier 5 and denoted as circuit B.
Circuit B has A.sub.in is its input and A.sub.out as its output. The input-output characteristic of circuit B is such that the potential at A.sub.out falls when the potential at A.sub.in rises, and the potential at A.sub.out rises when the potential at A.sub.in falls.
Circuit A can be viewed as having node N.sub.2 as its input and node N.sub.1 as its output. Circuit A then has a similar input-output characteristic: the potential at node N.sub.1 falls when the potential at node N.sub.2 rises, and rises when the potential at node N.sub.2 falls.
Circuit A and circuit B are cross-coupled: the input node of each is coupled to the output node of the other. They therefore operate at a point where their input-output characteristics intersect, but due to the similarity of their characteristics, the point of intersection may not be uniquely defined. This can cause the sense circuit 2 to oscillate between two operating points.
The cross-coupled configuration in FIG. 1 is furthermore similar to the configuration of a latch comprising two inverters coupled in a loop. The sense circuit 2 has a corresponding tendency to latch up, remaining in the high or low output state regardless of changes in current at the input terminal IN.
Another problem is that a large output voltage swing at the output terminal OUT entails a large swing at the input node A.sub.in of the inverting amplifier 5, hence at its output node A.sub.out, increasing the gain of the positive-feedback loop. The output voltage swing accordingly cannot be designed independently of the loop gain; the one depends on the other.
A further problem with the conventional sense circuit 2 becomes evident when it is used in a DRAM having a page mode, in which a word line remains active while memory cells in different columns on that word line are accessed. During such page access, at first the voltage swings on the bit lines are small, and only slight changes occurs in the current flowing on the data line DL. As access to the same word line continues, however, the voltage swings on the bit lines increase, with corresponding larger changes in current flow on the data line DL. If the load P-MOSFET 3a is designed for reliable sensing of small current changes on data line DL, then when the current changes become larger, P-MOSFET 3a may begin to saturate, allowing unwanted large potential changes on data line DL. That is, the sense circuit 2 has inadequate dynamic range for page-mode operation in a DRAM.
The dynamic range can be widened by using an N-MOSFET with interconnected gate and drain as the load transistor. If this type of load is employed, however, it becomes impossible to bias the data line DL close to V.sub.CC. This leads to problems regarding operating speed and operating margin, particularly at low supply voltages.